Optimized Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients using Wallace Multiplier

Authors:VASAMSETTI SUBRAHMANYAM, M. DEVI SATYA PRIYA

0624-0627

Programmable MBIST Design for Efficient In-Field Testing of FIFO Buffers in NoCs

Authors:BATHINI SANDHYA RANI, M. MUNI PRAVEENA RELA, G. SWETHA

0628-0633

An Efficient Novel Precharge-Free, Low-Power Content-Addressable Memory

Authors:SAKE SURESH BABU, K. GEETHA

0634-0640

Design and Implementation of Variable Latency Speculative Han-Carlson Adder using Verilog

Authors:G. SREEVENI, V. PRASAD

0641-0645

Implementation of FIR Digital Filters for Odd Length using Power Reduction Technique

Authors:T. NARMADA, G. SRIDEVI

0646-0650

Multi Bit Errors Detection and Correction using SRAM Based DMC

Authors:G. ROJA RANI, V. SOWMYA

0651-0656

An Advanced Traffic Light Controller using Verilog HDL

Authors:T. BALA OBULA REDDY, V. SOWMYA

0657-0661

Design and Implementation of Multi Key Distribution Server Based Data Security Scheme for RFID system

Authors:V. SUJANA, V. SOWMYA

0662-0666

Design of High Speed Variable Latency 64-Bit Carry Skip Adder

Authors:M. PAVITRA, CH. SRAVANI

0667-0672

An Design of Low-Power and Delay Hardware-Efficient FIR Filter Using Constant Multipliers

Authors:KOLLI MANIKUMARI, P. K. SURESH

0673-0678